DDR5 DDR4 LPDDR5 Combo PHY Silicon Proven IP Cores in 12FFC China

全球独立的半导体IP供应商和授权专业公司T2MIP高兴地宣布，来自其伙伴的DDR5/DDR4/LPDDR5组合PHY IP经过12FFC工艺（12nm FinFET Compact）验证，其配套的DDR5组合控制器IP设计来自于量产芯片组，客户可立即在T2M公司获得IP授权。

 DDR5/DDR4/LPDDR5 Combo PHY IP的模块化设计能够便捷地集成到现有的各种芯片架构，可以以最小的延时获得5400MT/s的吞吐速率。值得一提的特有功能包括输出阻抗的可编程化（DS）和晶粒上端侧阻抗的可编程化（ODT）。DDR5 Combo PHY IP和配套控制器IP符合DFI 5.0版本规范的要求，最高支持16个AXI端口，数据带宽可达512位。

 DDR5/DDR4/LPDDR5组合PHY IP核可以配置为DDR4、DDR5和LPDDR5模式。对于不同的DDR规格（DDR5、DDR4和LPDDR5），这个设计可支持的控制器最高时钟频率为675MHz、400MHz和600MHz。如果配置为DDR5的模式，DRAM数据速率为5400MT/s；如果配置为DDR4的模式，DRAM数据速率为3200MT/s；如果配置为LPDDR5的模式，DRAM数据速率为4800MT/s。根据应用场景的不同，这个设计可以支持CA/DQ X16/DQ X8/ZQ和其他四种模块的初始化设置，12FFC技术支持ZQ校准功能和各CA模块4种级别的电源配置。


 DDR5/DDR4/LPDDR5组合控制器IP核符合DDR5 JESD79-5和JESD79-5标准规范，交付件包括详细地说明操作指导，在设计时易于使用并且可以灵活配置。这个设计可以按照DDR5、DDR4和LPDDR5的配置采用不同的时钟频率，另外还支持最大省电模式（MPSM）、预充电命令模式、错误检查和纠正（ECC），重新排序功能、自刷新和下电处理等功能。这个设计支持PHY模块的内部自动配置功能，可以支持高达64GB的存储颗粒密度，以及X4、X8和X16的设备格式。

 半导体设计行业可采用这个DDR5 Combo PHY IP与配套的控制器IP设计芯片，用于企业级计算、区域存储网络、嵌入式系统、图形设备和其他消费电子产品。

 除了DDR5 IP核，T2M广泛的硅接口IP核组合包括USB、HDMI、DP、MIPI（CSI、DSI、UniPro、UFS、Soundwire、I3C）、PCIe、10/100/1000以太网、V by One、可编程SerDes、SD/eMMC、串行ATA和更多的IP核，这些设计在主流制造厂的工艺节点可达7nm,并且可以根据客户的具体要求定制或者移植到其他晶圆厂的相应工艺节点上生产。

 可用性：这些半导体IP可以立即进行客户授权，既可以单独授权，也可与预集成的控制器和PHY组合授权。有关授权的选择和报价等更多信息，请发送邮件至contact@t-2-m.com，进行了解。

 关于T2M：T2MIP是全球独立的半导体专业授权技术公司，提供复杂的半导体IP、软件、KGD和颠覆性技术，帮助客户加速开发可穿戴设备、物联网、通信、存储、服务器、网络、电视、机顶盒和卫星SoC。欲了解更多信息，请访问：www.t2m-ip.cn

Comments

Post a Comment

Popular posts from this blog

USB 3.0, PCIe 2.0, SATA 3.0 Combo PHY IP Cores Next Gen Chipsets

Image
  T2M IP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s Silicon Proven and mature USB 3.0, PCIe 2.0 and SATA 3.0 PHY IP Cores with a successful mass production track record in 22nm Ultra Low Power and 8nm advanced process technology in a wide range of major Fabs . This advanced PHY IP is poised to revolutionize data transfer solutions with its versatile compatibility and power-efficient design, making it ideal for a wide range of applications, from consumer electronics to high-performance computing systems. Licensed to a host of Global customers, the Combo PHY IP cores integrates three essential high-speed interface standards: USB 3.0, PCIe 2.0, and SATA 3.0 offering extensive compatibility, meeting the full specifications of each protocol. This integration not only enhances device connectivity but also simplifies system design and reduces overall cost. This wide-ranging compa
Read more

HDMI 2-0 Rx PHY IP Cores in 12FFC process Technology with matching Controller

Image
  T2M-IP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce its HDMI 2.0 Rx PHY IP cores , Silicon Proven in 12FFC process technology along with matching Controller IP   Cores   available immediately for licensing. The HDMI 2.0 Rx IP cores provides a best-in-class Receiver functionalities for a lossless display interface in ultra-high-definition multimedia SoCs.   This HDMI 2.0 Rx PHY IP Cores in 12FFC with matching Controller IP cores confirms with HDMI standard version 2.0b and offers a full HDMI receiver capability. It is made up of two modules: a link module and a physical layer (PHY). The link module is implemented as a synthesizable soft IP core, whereas the PHY IP core is fully compatible with DVI receiver and implemented as a hard IP based on 28HPC+ CMOS logic process. The transmission of audio-visual material is secured by an integrated HDCP (High-bandwidth Digital Content Protection) encryption. Keeping up with
Read more

MIPI CSI 2 Tx Rx Silicon Proven Controller IP Cores

Image
 T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s MIPI Alliance Standard MIPI CSI-2 v2.0 Tx and Rx Controller IP Cores for all types of High performance Camera applications. The CSI-2 Tx and Rx IP Cores are Production Proven and have been integrated with matching PHY’s in different process nodes in major Fabs. The MIPI Camera Serial Interface (CSI-2) is an interface between a camera and an image-processing engine. MIPI CSI Transmitter and Receiver adheres to MIPI CSI-2, MIPI D-PHY and MIPI C-PHY specification. The MIPI CSI-2 Transmitter along with MIPI CSI-2 Receiver and MIPI DPHY provides a complete solution for encoding MIPI data. The Layered architecture allows for 4 virtual configurable channels and Colour modes of 16, 18, 24 and 36 bpp. The Controllers can also support YUV420 8, YUV422 8, RGB 888, 565, 666, 555 & 444 and RAW 6, 7, 8, 10, 12 & 14 The MIPI CSI-2 v2.0 T
Read more