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Showing posts with the label JESD204B Tx and Rx Controller IP

Superfast Serial Interfacing with JESD204B Tx-Rx PHY IP Cores

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T2M IP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s Silicon Proven and mature JESD204B Tx & Rx PHY IP Cores in major Fabs in popular process nodes 14nm, 28nm and 40nm along with matching JESD204B Tx-Rx Controller IP Cores . The JESD204B offering has seen mass production in various chipsets. JESD204B Tx-Rx PHY IP Cores interface provides full support for the JESD204B synchronous serial interface, compatible with JESD204B.01 version specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. The JESD204B PHY has full featured transceiver capabilities along with standalone Tx and Rx availability. The PHY in 14nm, 28nm and 40nm supports a data rate of 1Gbps to 16Gbps per lane. The JESD204B PHY IP cores in 14nm, 28nm, 40nm supports multiple lanes transceiver, with this version including both receiver and transmitter. It is al

JESD204B Rx Tx Silicon Proven PHY Controller IP Core

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T2MIP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s JEDEC compliant JESD204B Tx and Rx Controller IP Core and JESD204B Tx and Rx SerDes PHY IP Core in 28HPC+ and 40LL nodes which are silicon proven in major Fabs for all High-Density, High-Speed Interface applications. JESD204B Rx-Tx PHY and Controller IP Core is a mechanism to achieve high-speed inter-device data transfers and deterministic latency across the serial link. JESD204B is a new 12.5 Gbps and 16Gbps serial interface standard for high-speed, high-resolution data converters which provides full support for the JESD204B synchronous serial interface, compatible with JESD204B.01 version specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices.   The JESD204B Tx and Rx SerDes PHY IP Core in 28HPC+ and 40LL process technologies are embedded with Multiple lanes with data rate f