JESD204B Rx Tx Silicon Proven PHY Controller IP Core
T2MIP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s JEDEC compliant JESD204B Tx and Rx Controller IP Core and JESD204B Tx and Rx SerDes PHY IP Core in 28HPC+ and 40LL nodes which are silicon proven in major Fabs for all High-Density, High-Speed Interface applications. JESD204B Rx-Tx PHY and Controller IP Core is a mechanism to achieve high-speed inter-device data transfers and deterministic latency across the serial link. JESD204B is a new 12.5 Gbps and 16Gbps serial interface standard for high-speed, high-resolution data converters which provides full support for the JESD204B synchronous serial interface, compatible with JESD204B.01 version specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. The JESD204B Tx and Rx SerDes PHY IP Core in 28HPC+ and 40LL process technologies are embedded with Multiple lanes with data rate f