T2M IP Complex Semiconductor Silicon IP Cores Company

T2M-IP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce its 12bit 5Gsps Current Steering DAC IP Core which is Silicon Proven in 28HPC+ process technology is available immediately for licensing. The DAC uses a proprietary architecture and self-calibration to achieve a higher accuracy or to increase yields with a very small area. A binary digital input code is translated into a quantized (discrete step) analogue output by the DAC. A reference quantity (either a voltage or a current) is split into binary and/or linear fractions to produce the output. The output is then generated by driving switches with a suitable number of current steering digital-to-analog converters to combine these fractions. The size and quantity of the fractions represent the range of potential digital input codes, which depends on the converter resolution or the input code's bit count (N)... For N bits, there are 2 possible codes. The analog output

  T2M-IP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce its 10-Bit 3-Msps Ultra Low Power SAR ADC IP Core which is Silicon Proven in 28HPC+ process technology is available immediately for licensing. The ADC uses a proprietary architecture that reduces harmonic and intermodulation distortions at high output frequency and amplitudes making it a truly lossless Analog IP  Core. The 10-Bit 3-Msps Ultra Low Power SAR ADC IP Core is High performance technology with 10-bit resolution, 3-Msps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core for leading edge systems on chip (SoCs) for microcontrollers, medical applications, and General purpose ICs. A digital signal that is discrete in both time and amplitude is created from an analogue signal that is continuous in both time and amplitude by an analog-to-digital converter. The 10 Bit 3 Msps Ultra Low Power SAR ADC IP Core employs a high-performance architecture and provid

T2M IP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the availability of its partner’s  silicon and production-proven 14-bit Wideband Time-Interleaved Pipeline ADC IP cores supporting 4.32 Gsps sampling speed in 28nm FDSOI process with full modification rights and unlimited usage. The 14-bit, 4.32Gbps Pipeline ADC IP Cores, extracted from a Production Chipset, supports 60dB Signal Noise Ratio (SNR) with input frequencies ranging from 54MHz to 1.7GHz. They are used in a variety of applications, including audio applications, microcontrollers, high-speed STB, Wi-Fi, automotive, radar, and 5G applications.  The ADC IP Cores includes two internal power supply regulators (LDO) for the analog part: - A 1.1v LDO with an external decoupling capacitor to reach a high-power rejection ratio, - A 1.5v LDO with an internal capacitor for the input buffer and biasing The digital part is supplied by the external 1.0V. This ul

全球独立的半导体 IP 核供应商和技术专业公司 T2M IP 很高兴地宣布，其合作伙伴 14 位宽带时间交错流水线 ADC IP 核 的芯片设计通过 28 纳米 FDSOI 工艺的生产验证，支持 4.32Gsps 的采样速度。该 IP 核的交付件包括全套的源代码，授权客户可获得完全的修改权，以及无限次的使用权。  该 ADC 可以显著提升汽车电子相关技术的性能，例如汽车传感器和其他相关组件如果配置高采样率的 ADC ，可降低数据向处理器传输的延迟，实现实时的处理。特别是采样速率直接影响到激光雷达的系统性能，这也关系到 ADAS （高级驾驶辅助系统）的工作是否具有安全性和可靠性的最大保障。  这个 14 位京都的 ADC IP 核其采样速率为 4.32Gsps ，采用 Pipeline ADC 架构，已在主要芯片厂的主要工艺节点实现量产，支持 60dB 的信噪比（ SNR ），输入频率从 54MHz 到 1.7GHz ，涵盖了从汽车、微控制器到高速机顶盒、 Wi-Fi 、雷达和 5G 应用等广泛的应用。   ADC IP 核包括两个用于模拟部分的内部电源稳压器（ LDO ）。 Ø   一个 1.1v 的 LDO ，带有一个外部去耦电容，达到一个高功率抑制率。 Ø   一个 1.5v 的 LDO ，有一个内部电容用于输入缓冲和偏置。数字部分由外部 1.0v 供电。  Pipeline ADC IP 核是一个混合信号系统，它由采样和保持放大器（ SHA ）、乘法数模转换器（ MDAC ）、带隙电压基准、比较器、开关电容电路和偏置电路组成。它将系统级和电路级之间的所有规格联系在一起。有了这个设计流程，给定整体 ADC IP 核的规格，如分辨率、采样率、电压供应和输入信号范围，所有的微架构电路指标都能实现。  Pipeline ADC IP 核由几个连续的阶段组成。差分结构的第一级评估最重要的位（ MSB ）值，然后对信号进行调节，并将其传递给下一级进行 MSB-1 转换。每个阶段与其他阶段同时执行其操作。   T2 M 广泛的无线 IP 核 还包括 22nm ULL 的蓝牙双模式 v5.2 射频收发器 IP 核、 40/55nm 的 BLE v5.2 / 15.4 (0.5mm2) 射频收发器 IP 核、 40ULP 的 NB-IoT/C