DDR5/DDR4/LPDDR5 Combo PHY Silicon Proven IP Cores in 12FFC
T2MIP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s DDR5/DDR4/LPDDR5 Combo PHY IP Cores in 12FFC process nodes with matching DDR5 Combo Controller IP Cores which are silicon proven and has been extracted from production chips. The DDR5/DDR4/LPDDR5 Combo PHY IP Cores' hierarchical yet comprehensible design enables simple integration into any design architecture, offers minimal latency, and supports throughput of up to 5400MT/s. Programmable output impedance (DS) and Programmable on-die termination are available as unique features (ODT). The DDR5 Combo PHY IP Cores with matching Controller can support up to 16 AXI ports with data width up to 512 bits and is compliant with DFI version 5.0 Specification. The DDR5/DDR4/LPDDR5 Combo PHY IP Cores may also function independently in DDR4, DDR5, and LPDDR5 modes. With maximum controller clock frequencies of 675MHz, 400MHz, and