T2M IP Complex Semiconductor Silicon IP Cores Company

T2M-IP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce its best-selling  GbE (10/100/1000 Base-T) PHY IP Core’s   availability for immediate licensing as the final quarter of the Fiscal Year approaches. This popular Networking IP cores has a unique power usage and Size characteristic that helps in its simple integration into any Subsystem.  The  Gigabit Ethernet PHY IP Cores  is extracted from production chip is a highly integrated single chip for Giga 10/100/1000 Ethernet applications. It is an IEEE 802.3u/ab compliant single-port Giga Ethernet physical layer transceiver with low power consumption compared to market standards. It supports 10BASE-T, 100BASE-T, and 1000BASE-T operation. The GPHY connects the Media Access Control Layer (MAC) by GMII (Giga Media Independent Interface) or RGMII for an unobstructed network flow. The digital 1G Ethernet MAC, TSN MAC, and PCS Controller IP Cores can all be licenced together with

  全球独立的半导体 IP 核供应商和技术专业公司 T2M IP 很高兴地宣布，其合作伙伴的 MIPI D-PHY/LVDS 组合 PHY IP 核与配套的控制器 IP 在主流工厂的 40nm 工艺节点实现量产，支持客户采用该 IP 组合设计高可靠性的低功耗数据传输芯片组。 MIPI D-PHY/ LVDS 组合 PHY IP 核 针对低功耗方式下的高带宽数据通信应用需求。支持 GVI 、 LVDS 或 MIPI DSI 的接口要求，根据芯片的规格配置，可成为 D-PHY 或 LVDS 的组成部分。在 GVI/LVDS 应用方式下，由 IP 核构成的宏模块包含多个发送通道和一个 SU 单元。发送通道的宏模块可以配置为 GVI （ CML ）或 LVDS 模式；在 MIPI D-PHY 应用方式下，宏模块由一个时钟通道和四个数据通道构成。 配合 DPHY 和 LVDS 的直流耦合或 GVI 的交流耦合技术， MIPI D-PHY/ LVDS 组合 PHY IP 核 支持每个通道的并行接口配置为 10 位 /9 位 /8 位 /7 位，还支持 0~9dB 范围的 2 抽头 FFE （前馈均衡）编程。 DPHY IP 核可以以一个时钟通道和四个数据通道支持双向的数据传输，同时实现 RX 处理和 CD 机制的低功耗指标。这个 IP 核可实现的数据速率范围是： GVI ： 0.5Gbps~4.0Gbps ； LVDS ： 0.25Gbps~2.0Gbps 。 D-PHY IP 核： 187.5Mbps~1.5Gbps （高速）和 10Mbps （低功耗）。 这个 40nm 工艺的 D-PHY/LVDS Combo PHY IP 核可采用单一的 PLL 电路实现所有通道的信号处理，即噪声环境下受干扰信号的检测、均衡、调制 - 解调、滤波和恢复。 Combo PHY 具有嵌入的 BIST 电路，支持线键 bonding 的 封装工艺。该 IP 核的参考时钟电路频率可进行变成配置，将每个数据通道的启用或关闭进行单独管理，实现的待机功耗非常低。 MIPI D-PHY/LVDS 组合 PHY IP 核 已被用于半导体行业的智能手机、汽车摄像头、数字电视、掌上电脑、个人电脑、虚拟广告屏幕和其他工业用途。 除了 40nm 的 MIPI D-PHY/LVDS 组合 P

  T2M IP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s mature and silicon proven MIPI D-PHY/LVDS Combo PHY IP Cores in 40nm in major Fabs along with matching Controller IPs. The MIPI/ LVDS combo Core has been in multiple productions resulting in low power chipsets with very reliable data transmission. The MIPI D-PHY/ LVDS Combo PHY IP Cores is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can be easily fabricated and implemented in a GVI, LVDS or MIPI DSI system. The DPHY/LVDS Combo PHY IP cores is able to function as a D-PHY or LVDS according to the need of the user. For GVI/LVDS system, Macro consists of multi-transmitter channels and one SU unit. The transmitter macro can be configured to GVI (CML) or LVDS mode. For MIPI D-PHY system, the configuration includes a Clock Lane Module and four Data Lane Module