14-Bit 4.32 Gs/Ps 1.7GHz BW Time-Interleaved Pipeline ADC IP Cores

T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the availability of its partner’s silicon and production-proven 14-bit Wideband Time-Interleaved Pipeline ADC IP cores supporting 4.32 Gsps sampling speed in 28nm FDSOI process with complete source-code delivery and full modification rights and unlimited usage.

Automotive Applications such as sensors and other components need a high sampling rate to reduce the latency in data transfer and behave in real-time for the same. Data converters perform a key role in improving automotive applications such as Lidar which needs ultra-high sampling rate for ADAS (Advanced Driver-Assistance System) to work with utmost safety and reliability. 

 The 14-bit, 4.32Gsps Pipeline ADC IP Cores is extracted from a production chipset, supporting a 60dB Signal to Noise Ratio (SNR) with an input frequency ranging from 54MHz to 1.7GHz, that covers a wide range of applications ranging from Automotive, Microcontrollers, to High-speed STB, Wi-Fi and, Radar and 5G applications.

The ADC IP Cores include two internal power supply regulators (LDO) for the analog part:

 Ø  A 1.1v LDO with an external decoupling capacitor to reach a high-power rejection ratio,

Ø  A 1.5v LDO with an internal capacitor for the input buffer and biasing the digital part is supplied by the external 1.0V.

Pipeline ADC IP Cores is a mixed-signal system, which consists of a sample and hold amplifier (SHA), multiplying digital-to-analog Converter (MDAC), bandgap voltage reference, comparator, switch-capacitor circuits, and biasing circuits. It links all the specifications between the system levels and circuit levels together. With this design flow, if the overall ADC IP Cores specifications are given, such as resolution, sampling rate, voltage supply, and input signal range, all the sub-block circuitry specifications are achieved.

A pipeline ADC IP Cores consists of several consecutive stages. The differential structured first stage evaluates the most significant bit (MSB) value and then conditions the signal and passes it on to the next stage for an MSB-1 conversion. Each stage executes its operation concurrently with the other stages.

T2M’s broad Wireless IP cores also include  Bluetooth Dual mode v5.2 RF Transceiver IP Cores in 22nm ULL, BLE v5.2 / 15.4 (0.5mm2) RF Transceiver IP Cores in 40/55nm, NB-IoT/Cat M UE RF Transceiver IP Cores in 40ULP, Sub6 GHz RF Transceiver IP Cores, all can pe ported to other nodes and foundries as per the customer requirements.

Availability: These Analog Data convertors’ IP cores are available for immediate licensing. For further information on licensing options and pricing please drop a request at: contact.

About T2M: T2M-IP is the global independent semiconductor technology expert, supplying complex semiconductor IP Cores, Software, KGD, and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB, and Satellite SoCs. For more information, please visit: www.t-2-m.com

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