体验 DDR5 DDR4 LPDDR5 Combo PHY 和配套匹配控制器 IP 核的无缝 RAM 接口速度

全球独立的半导体 IP 核供应商和技术专业公司 T2MIP 很高兴地宣布，其合作伙伴 DDR5/DDR4/LPDDR5 Combo PHY IP 12FFC 工艺节点的IP核与配套的 DDR5 Combo 控制器 IP 核可立即供货，这些从生产芯片中提取的IP 核已经过硅验证。

DDR5/DDR4/LPDDR5 Combo PHY IP 核结构化的设计使其可方便地用于任何设计架构，提供低延迟并实现高达 5400MT/s 的吞吐量。它拥有可编程的输出阻抗 (DS) 和可编程的片上终端 (ODT) 特殊功能。该 DDR5 Combo PHY 及匹配的控制器符合 DFI 5.0 版规范，可以支持多达 16 个 AXI 端口，且数据宽度高达 512 位。

该 DDR5/DDR4/LPDDR5 Combo PHY IP 核也能够在 DDR4、DDR5、LPDDR5 模式下单独运行。该工艺技术可支持各种 DDR5/DDR4/LPDDR5 标准，最大控制器时钟频率为 675MHz、400MHz、600MHz，最大 DRAM 数据速率可达到 5400Mt/s (DDR5)、3200MT/s (DDR4)、4800MT/s (LPDDR5)。该产品可支持四个模块，便于进行灵活配置 CA/DQ_X16/DQ_X8/ZQ。12FFC 技术具有 ZQ 校准的附加功能，且每个 CA 模块可支持 4 个等级，对功耗有不同的考虑，其核心功率的工作电压为 0.8V。


该 DDR5/DDR4/LPDDR5 Combo 控制器 IP 核具有功能齐全、便于使用且可合成的设计，且与 DDR5 JESD79-5 和 JESD79-5 规范兼容。该核符合 DDR5、DDR4 和 LPDDR5 的不同时钟频率。该核还支持 PHY 内部自动决策，并具有其他相关功能，如最大省电模式 (MPSM)、预充电命令模式、错误检查和纠正 (ECC)、重新排序交易等，可实现更高的性能以及完成自动刷新和关闭电源操作。该核能够支持高达 64GB 的设备密度和 X4、X8、X16 设备类型。

DDR5 Combo PHY IP 核和 DDR5 Combo 控制器 IP 核已用于半导体行业的企业计算、存储区域网络、嵌入式系统、图形设备和其他消费电子产品……

除了 DDR5 IP 核，T2M 广泛的硅接口 IP 核系列产品还包括 USB、HDMI、显示端口、MIPI（CSI、DSI、UniPro、UFS、Soundwire、I3C）、PCIe、10/100/1000 以太网、V by One、可编程 SerDes、SD/eMMC、串行 ATA 和更多的 IP 核，可在主要工厂以低至 7 纳米的工艺尺寸来提供。这些产品还可以根据要求被移植到其他晶圆代工厂和前沿制程节点。

可用性：这些半导体接口 IP 核可立即获得许可，既可独立使用，也可与预集成的控制器和 PHY 一起使用。如需了解更多关于许可选件和价格的信息，请发送请求/邮件至

关于 T2M：T2MIP是一家全球性独立半导体技术专业公司，可提供复杂的半导体 IP 核、软件、KGD 和颠覆性技术，帮助您加速开发可穿戴设备、物联网、通信、存储、服务器、网络、电视、机顶盒和卫星 SoC。如需更多信息，请访问：www.t-2-m.com

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