T2M IP Complex Semiconductor Silicon IP Cores Company

  T2M IP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s 16G Multiprotocol SerDes PHY IP Core in 28HPC + process node which is silicon proven and in mass production with its superfast data transfer speed, low power and low die area providing a highly reliable system. The 16G Multiprotocol SerDes PHY IP Core supports PCIe 4.0 , JESD204B , 10G ethernet, rapid IO, and CPRI protocols. This allows the Serdes PHY to be implemented into a diverse range of applications based SoCs. Boasting a Low power and Low Die area, the PHY’s lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, with configurable low power mode, the PHY is widely applicable for various scenarios under different consideration of power consumption.  The multiple Protocols allows for the capability of handling various applicatio

T2MIP , the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s JEDEC compliant JESD204B Tx and Rx Controller IP Core and JESD204B Tx and Rx SerDes PHY IP Core in 28HPC+ and 40LL nodes which are silicon proven in major Fabs for all High-Density, High-Speed Interface applications. JESD204B Rx-Tx PHY and Controller IP Core is a mechanism to achieve high-speed inter-device data transfers and deterministic latency across the serial link. JESD204B is a new 12.5 Gbps and 16Gbps serial interface standard for high-speed, high-resolution data converters which provides full support for the JESD204B synchronous serial interface, compatible with JESD204B.01 version specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices.   The JESD204B Tx and Rx SerDes PHY IP Core in 28HPC+ and 40LL process technologies are embedded with Multiple lanes with data rate f

 T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s MIPI Alliance Standard MIPI CSI-2 v2.0 Tx and Rx Controller IP Cores for all types of High performance Camera applications. The CSI-2 Tx and Rx IP Cores are Production Proven and have been integrated with matching PHY’s in different process nodes in major Fabs. The MIPI Camera Serial Interface (CSI-2) is an interface between a camera and an image-processing engine. MIPI CSI Transmitter and Receiver adheres to MIPI CSI-2, MIPI D-PHY and MIPI C-PHY specification. The MIPI CSI-2 Transmitter along with MIPI CSI-2 Receiver and MIPI DPHY provides a complete solution for encoding MIPI data. The Layered architecture allows for 4 virtual configurable channels and Colour modes of 16, 18, 24 and 36 bpp. The Controllers can also support YUV420 8, YUV422 8, RGB 888, 565, 666, 555 & 444 and RAW 6, 7, 8, 10, 12 & 14 The MIPI CSI-2 v2.0 T

  T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s MIPI Alliance compliant MIPI UFS v3.1 Controller IP, MIPI UniPro v1.8 Controller IP and MIPI M-PHY v4.1 IP Cores in different process nodes for all UFS Device Solutions. The MIPI M-PHY v4.1 IP Core is the latest MIPI Feature Storage IP Solution SerDes PHY of M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. It supports serial interface technology with high bandwidth capabilities also HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY IP Core, compliant to the RMMI interface which allows UniPro controller and UFS Controller. It provides robust testability by Low operation current and low standby current Build-In-Self-Test (BIST), and receiver eye data monitorin